| AN IMPROVED SECURE SCAN DESIGN FOR SCAN-BASED DIFFERENTIAL CRYPTANALYSIS ATTACK | |
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MSRDG International Journal of Computer Scientific Technology & Electronics Engineering
© 2026 by MSRDG IJCSTEE Journal Volume 2 Issue 1 Year of Publication: 2026 |
Paper Download Article ID MSRDG-IJCSTEE-V2I1P103 |
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Abstract: Scan-based testing is an indispensable technique for ensuring the functional correctness of modern digital integrated circuits (ICs). However, the scan infrastructure, while essential for manufacturing test, simultaneously creates a significant security vulnerability by providing an accessible pathway for adversaries to perform differential cryptanalysis attacks. Through controlled scan-in and observation of scan-out data, an attacker can systematically extract secret cryptographic keys embedded within the circuit under test (CUT). This paper proposes an improved secure scan design methodology that effectively mitigates scan-based differential cryptanalysis attacks while preserving acceptable fault coverage. The proposed architecture integrates a Linear Feedback Shift Register (LFSR)-based dynamic key generation module with a two-phase authentication protocol and a reconfigurable multiplexer-controlled scan segment obfuscation scheme. The design employs a challenge-response authentication mechanism prior to granting scan access, thereby preventing unauthorized interrogation of the scan chain. Experimental evaluations conducted on ISCAS-89 and ITC-99 benchmark circuits demonstrate that the proposed method reduces the differential cryptanalysis attack success rate to 3.7%, representing a 94.8 percentage-point improvement over conventional scan designs, while incurring only 7.4% area overhead and 5.8% power overhead. A fault coverage of 91.8% is maintained under the highest security configuration, confirming that the proposed scheme achieves a favourable security-testability trade-off superior to existing countermeasures. |
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| Keywords: Scan-based testing, Differential cryptanalysis, Secure scan design, LFSR key generation , Hardware security , Test access mechanism , Scan obfuscation | |
